Digital downconverter design

There are cases when filter orders are the main design constraint. You use the DDC object to design decimation filters with a specified order by setting the MinimumOrderDesign property to false. You can still specify the required passband and stopband frequencies of the cascade response.

Note however that the stopband attenuation and ripple are now controlled by the order of the filters and not by property values. The DDC object designs a numerically controlled oscillator based on a small set of parameters. Set the Oscillator property to 'NCO' to choose a numerically controlled oscillator. Use 32 accumulator bits, and 18 quantized accumulator bits. Set the center frequency to You can set different properties on the DDC object to control the fixed-point data types along the down conversion path.

Cast the word and fraction lengths at the input of each filter to 20 and 19 bits respectively by setting the CustomFiltersInputDataType property to numerictype [],20, Initialize a sine wave generator to simulate a GSM source. Initialize a buffer to cast the input signal data type to 19 bits word length and 18 bits fraction length.

Configure figures for plotting spectral estimates of signals. The DDC object allows you to obtain down converter designs in one simple step.

It provides tools to design decimation filters that meet passband frequency, passband ripple, stopband frequency, and stopband attenuation specifications. The DDC object also provides convenient tools to visualize and analyze the decimation filter responses. Choose a web site to get translated content where available and see local events and offers. Based on your location, we recommend that you select:. Select the China site in Chinese or English for best site performance. While the mixer and local oscillator sections are quite similar for all DDCs, the best filter design depends on the filter bandwidth.

For wideband channels, a conventional FIR filter, as shown in Figure 1, is best. For applications requiring several dozen or even hundreds of channels, this approach can become impractical. Because of the extremely fine resolution of its NCO tuning frequency, a true DDC can translate any input frequency component down to 0 Hz, often with bit accuracy. This ability makes DDCs ideal for applications that require precise changes in tuning such as in continuous Doppler correction for satellite tracking systems.

However, in other applications, a channelizer approach may be sufficient. This is a bank of equally spaced, fixed frequency band-pass filters whose outputs are translated to baseband 0 Hz. One crude example of a channelizer familiar to everyone is a simple FFT. It converts a block of N time samples equally spaced in time into block of N frequency samples equally spaced in frequency.

For a continuous stream of input time sample blocks, samples at a given point in successive output blocks represent a translated, bandpass frequency signal or bin. By selecting the output of a particular bin, a channelizer can serve as a primitive DDC, but with extremely coarse tuning resolution that is determined by the number of points in the FFT as shown in Figure 2.

Another serious limitation of the FFT as a DDC is the frequency response passband flatness of the bin, and rejection of energy from adjacent bins stop-band rejection. Other channelizer designs use various digital filtering techniques to split the bands with better flatness and adjacent channel rejection, but they usually require significantly more hardware than an FFT for a comparable number of bins.

Regardless of its design, the tuning resolution of any channelizer is simply equal to the number of bins or channel filters. As a result, channelizers may be useful for spectrum analyzers, scanners, and energy survey equipment but they are rarely used as substitutes for DDCs in software radio communication systems.

Therefore, we embarked on a mission to a new signal processing architecture for a narrowband DDC with 64 channels or more; with full tuning resolution, but with much more efficient use of FPGA resources than deploying a farm of conventional DDC cores.

Each conventional DDC requires its own local oscillator phase accumulator and sine table , mixer two multipliers , and FIR filter multipliers and accumulators.

Since this is the same clock range rating for commercial DDC IP cores, all of the hardware resources used for each channel must be dedicated to that channel. However, imagine that the input data sample rate is reduced by a factor N. By operating the DDC hardware resources required for one channel at the full clock rate, those same resources can then be multiplexed time-shared across N channels.

Of course, provisions must be made for buffering the data for all channels while multiplexing. One way to achieve this input rate reduction is to split the input signal into a bank of N adjacent frequency bands using a channelizer.

Then, the output sample rate for each band can be reduced by a factor of N. The output from the band containing the signal of interest can be selected as the input to any given DDC to fine-tune within that band. The tradeoff question becomes: Are the resources freed up by multiplexing the DDCs more than the resources required for the channelizer? In order to understand how the input tones are processed, it is important to understand that the signal first passes through the NCO, which shifts the input tones in frequency, then passes through the decimation, optionally through the gain block, and then optionally through the complex to real conversion.

It is important to understand the macro view of the signal flow through the AD as well. This is illustrated by the block diagram of the AD shown in Figure 4. With an input sample clock of The second harmonic of the input frequency will alias into the first Nyquist zone at This is illustrated by the plot of the Frequency Folding Tool in Figure 5.

The first processing block that the signal passes through in the AD is the NCO that will shift the spectrum to the left in the frequency domain by 98 MHz recall our tuning frequency is 98 MHz. This will shift the analog input from What is interesting is that we see an unexplained tone in the FFT. However, is this tone really unexplained? The NCO is not subjective and shifts all frequencies.

In this case, it has shifted the alias of the fundamental input tone 98 MHz down to 0. In addition, yet another tone has been shifted as well and appears at Where did this tone actually come from? Well, the answer is no … and yes. This dc offset results in a tone present at dc or 0 Hz. In the actual output of the AD, the dc offset tone at 0 Hz is shifted down in frequency to —98 MHz.

Due to the complex mixing and decimation, this dc offset tone folds back around into the first Nyquist zone in the real frequency domain. When looking at a complex input signal where a tone shifts into the second Nyquist zone in the negative frequency domain, it will wrap back around into the first Nyquist zone in the real frequency domain.

Since we have decimation enabled with a decimation rate equal to two, our decimated Nyquist zone is The dc offset tone is shifted to —98 MHz, which is 5. When this tone folds back around into the first Nyquist zone it ends up at the same offset from the Nyquist zone boundary in the real frequency domain, which is